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Vulnerabilities

Vulnerability · CVE-2025-63384

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the

Published Nov 10, 2025 · catalog updated Nov 12, 2025 · A vulnerability was discovered

Last checked Oct 28, 2026. A connected source was read within the last 7 days.

Check if you run it

No confirmed exploitation is on record for CVE-2025-63384. EPSS is 0.33%. Act only if a listed version of A vulnerability was discovered is installed.

Gaps on this record

  • The stored product name is a package slug. The name on this page is taken from the title (A vulnerability was discovered).
  • No version range is stored. A customer cannot check an installed version against this record.
  • No vendor fix or required action is stored. Compare the linked advisory before you change production.

Same product and reporting

Severity
Medium6.5
Known exploitation
Not in CISA/VulnCheck KEV
EPSS
0.33%
Remediation
Vendor / distro source
Affected products
vendor n/a n/a n/a

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.

Are you affected?

Enter the version you run. The result uses only the ranges stored on this record.

The check returns affected, not affected, or incomplete. It does not guess a version that is missing from the record.

  • vendor n/a n/a n/an/a

How to fix CVE-2025-63384

  • No stored fix

    No vendor fix text is stored. Use the linked advisory before you change production.

  • Version check

    No version range is stored, so an installed version cannot be checked on this page.

  • Advisory

    Open the cve_org record and follow its fix.

  • Official advisories

What to do

Three questions, each answered from this record only. Confirm the vendor advisory before you patch.

Should you patch?

No confirmed exploitation is on record for CVE-2025-63384. EPSS is 0.33%. Act only if a listed version of A vulnerability was discovered is installed.

Which versions are affected?

Compare what you have installed with n/a n/a n/a n/a. Compare the installed version with the linked vendor advisory before you change production.

What should an analyst verify?

No weakness class is stored. EPSS 0.33%. There is no CISA KEV listing. No Exploit-DB or Metasploit reference is linked. Use the source links for the original advisory.

Code

The project this record applies to. Exploit listings stay in References.

Timeline

Detection, updates, and resolution for this record.

  1. Nov 10, 2025 · EUVD

    Detected

    A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege

  2. Nov 12, 2025 · EUVD

    Updated

    A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege

Sources

  • CVE.orgVulnerability recordCVE-2025-63384

    Official CVE identifier

    cve.org
  • EUVDVulnerability recordEUVD-2025-50785

    A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S

    euvd.enisa.europa.eu

References

Freshness

Last verified in this catalog Oct 28, 2026. Significant claims (KEV, EPSS, CVSS, affected ranges) come from the source rows above — open the original publisher for the authoritative advisory.

  • CVE.orgOct 25, 2026
  • EUVDOct 25, 2026