Vulnerability · CVE-2026-29644
XiangShan (open-source high-performance RISC-V processor) commit edb1dfaf7d290ae99724594507dc46c2c2125384 (2024-11-28) has improper gating of its distributed CSR write…
Published Apr 21, 2026 · catalog updated Jun 17, 2026 · the affected product
Last checked Oct 31, 2026. A connected source was read within the last 7 days.
Check if you run it
No confirmed exploitation is on record for CVE-2026-29644. EPSS is 0.10%. Act only if a listed version of the affected product is installed.
Gaps on this record
- No plain product name is stored. The page cannot tell you which product to check.
- No version range is stored. A customer cannot check an installed version against this record.
- No vendor fix or required action is stored. Compare the linked advisory before you change production.
- Severity
- Medium5.3
- Known exploitation
- Not in CISA/VulnCheck KEV
- EPSS
- 0.10%
- Remediation
- Not established
- Affected products
- See sources for product scope
XiangShan (open-source high-performance RISC-V processor) commit edb1dfaf7d290ae99724594507dc46c2c2125384 (2024-11-28) has improper gating of its distributed CSR write-enable path, allowing illegal CSR write attempts to alter custom PMA (Physical Memory Attribute) CSR state. Though the RISC-V privileged specification requires an illegal-instruction exception for non-existent/illegal CSR accesses, affected XiangShan versions may still propagate such writes to replicated PMA configuration state. Local attackers able to execute code on the core (privilege context depends on system integration) can exploit this to tamper with memory-attribute enforcement, potentially leading to privilege escalation, information disclosure, or denial of service depending on how PMA enforces platform security and isolation boundaries.
No affected version ranges are stored yet. Use the vendor advisory before you decide this record does not apply.
How to fix CVE-2026-29644
No stored fix
No vendor fix text is stored. Use the linked advisory before you change production.
Version check
No version range is stored, so an installed version cannot be checked on this page.
Advisory
Open the cve_org record and follow its fix.
Official advisories
What to do
Three questions, each answered from this record only. Confirm the vendor advisory before you patch.
Should you patch?
No confirmed exploitation is on record for CVE-2026-29644. EPSS is 0.10%. Act only if a listed version of the affected product is installed.
Which versions are affected?
Affected version ranges are not on this record. Compare the installed version with the linked vendor advisory before you change production.
What should an analyst verify?
CWE-284: Improper Access Control. EPSS 0.10%. There is no CISA KEV listing. No Exploit-DB or Metasploit reference is linked. Use the source links for the original advisory.
Code
The project this record applies to. Exploit listings stay in References.
Timeline
Detection, updates, and resolution for this record.
Apr 21, 2026 · NIST NVD
Detected
XiangShan (open-source high-performance RISC-V processor) commit edb1dfaf7d290ae99724594507dc46c2c2125384 (2024-11-28) has improper gating of its distributed CSR write-enable path, allowing illegal CSR write attempts to alter custom PMA (Physical Memory Attribute) CSR state. Though the RISC-V privileged specification requires an illegal-instruction exception for non-existent/illegal CSR accesses,
Jun 17, 2026 · NIST NVD
Updated
XiangShan (open-source high-performance RISC-V processor) commit edb1dfaf7d290ae99724594507dc46c2c2125384 (2024-11-28) has improper gating of its distributed CSR write-enable path, allowing illegal CSR write attempts to alter custom PMA (Physical Memory Attribute) CSR state. Though the RISC-V privileged specification requires an illegal-instruction exception for non-existent/illegal CSR accesses,
Sources
- CVE.orgVulnerability recordCVE-2026-29644
Official CVE identifier
cve.org - FIRST EPSSExploitation probabilityCVE-2026-29644
30-day exploitation probability 0.10%
first.org - NIST NVDVulnerability recordCVE-2026-29644
XiangShan (open-source high-performance RISC-V processor) commit edb1dfaf7d290ae99724594507dc46c2c2125384 (2024-11-28) has improper gating of its distributed CSR write-enable path, allowing illegal CSR write attempts to alter custom PMA (Physical Memory Attribute) CSR state. Thou
nvd.nist.gov
References
Freshness
Last verified in this catalog Oct 31, 2026. Significant claims (KEV, EPSS, CVSS, affected ranges) come from the source rows above — open the original publisher for the authoritative advisory.
- FIRST EPSSOct 31, 2026
- CVE.orgOct 16, 2026
- NIST NVDOct 15, 2026